In the manufacture of integrated circuit chips it is an established practice that arrays of chips are formed together on a single substrate, which is often termed a wafer in the art. In general, each chip is formed with a circuit array on one face and the substrate is diced or cut by a suitable apparatus in order to separate the individual chips from one another.
Throughout this specification reference to an integrated circuit chip shall be taken as a integrated circuit chip formed from a suitable semiconductor substrate, where the circuit is formed on one face and/or within the material of the substrate adjacent to one face, and the term circuit array shall be taken as the electrical circuit of an integrated circuit chip which is formed on and/or within that one face. It will therefore be appreciated that in the case of a ball grid array type of integrated circuit chip, the term “circuit array” of the chip will be taken to mean the face containing the ball grid array.
In the past difficulties have existed in efficiently and cost-effectively transferring cut (diced) chips from the dicing station to an output, while accurately maintaining position of the chips throughout the transfer process to prevent misalignment of the chips at the output. It is important that the chips be presented to the output in a predetermined position and with the circuit array accessible, to enable an adequate visual inspection of the individual chips prior to packaging.
One practice in the known art has been to apply an adhesive tape to the non-circuit face of the substrate prior to dicing, and then on completion of the dicing process to remove the chips from the tape. This procedure, however, has presented difficulties in the past, which difficulties are disclosed in U.S. Pat. No. 6,187,654 and U.S. Pat. No. 6,165,232, both incorporated in the present application by reference. An alternative procedure in the known art, as proposed in U.S. Pat. No. 6,187,654 and U.S. Pat. No. 6,165,232, also incorporated herein by reference, is to provide a nest which is utilized to support the substrate during the cutting process and to subsequently support the separated chips on completion of the cutting process to enable the chips to be washed, dried and delivered to the output. A difficulty with the use of nests as disclosed in these patents relates to the delay that occurs in the transfer of the chips from the dicing means to the output which transfer includes the washing of the chips within the nest and subsequently inspecting the resultant chips. This delay is primarily due to the use of the nests. In addition, each nest presents a significant capital expense which limits the number of nests which can be utilized at any one time. Moreover, chips of different physical size and aspect require different nests. Furthermore, the nests can be readily damaged in the dicing process, which requires replacement of the nest with the consequent capital costs.